Advanced Semiconductor Packaging


The challenges of 3D device integration in wafer scale packages require new measurement and defect inspection techniques to ensure robust yield. Advanced chip integration schemes that use microbumps, redistribution layers, TSVs and copper pillars, produce stringent requirements for precision in the formation of structures. ‘Top-down’, two-dimensional measurements alone cannot provide enough information.


Within the wafer-scale packaging market, 3D packaging is now the fastest growing segment for process control metrology, with TSV integration projected to grow at a steep rate over the next several years. Nanometrics metrology and inspection solutions offer a broad range of features to control micro bumps, redistribution layers and TSV patterning, etch and deposition processes, including measurement of critical dimensions (CD), registration and depth/height/profile.