While front-end development has pushed metrology into 3D measurements, the challenges of 3D integration of devices in wafer scale packages also has required new measurement and inspection techniques to ensure robust yield. The same external drivers, including the form factors of smart phones and tablet PCs as well as demand for higher bandwidth memory are driving overall chip package sizes to smaller footprints, with chips that consume less power.
To meet these requirements, chip packaging designers are developing vertical stacking techniques, bonding multiple chips together one on top of the other. To increase efficiency, manufacturers are eliminating wire bonding as the form of making electrical connections between chips and instead developing direct interconnect technologies which promise both better performance and lower energy consumption. The increased use and design of advanced multi-chip integration schemes that use microbumps, copper pillars, and TSVs produce stringent requirements for precision in shape, height, profile, pitch and overlay. Equally challenging are the requirements for wafer-on-wafer bonding, where process induced defects and other yield excursions can have expensive consequences.
Nanometrics helps manufacturers to meet these challenges with two advanced process control systems. Nanometrics UniFire tool offers customers a broad range of features to control their micro bump, redistribution layer(s), and TSV patterning, etch and deposition processes, including measurement of critical dimensions (CD), registration, and depth/height/profile, as well as the ability to measure wafer bow/shape and film thickness. Adding to the UniFire’s capabilities, Nanometrics now offers the capability to find process induced defects with its SPARK system, an ultra-fast inspection tool capable of finding defects associated with TSV formation, as well as wafer bonding, thinning and backside processing.
To understand the need for process control in advanced packaging consider the new 3D components introduced with new package designs (see figures below).
First generation stacked packages use ultra-thin wire to form the electrical connections between die, and solder balls to bond die together and to the PCB. New advanced packages create connections between die by creating tiny holes through each device (through silicon vias) filling the holes with copper, and forming many microbumps or pillars to create direct connections. Adding to the complexity, new layers to redistribute the contact I/Os to the microbumps are required to take better advantage of the full geometry of the top side of the chip.
These new layers distribute the contact points regularly instead of forcing them to the outside of the chip’s edges, as was done before flip chip (also known as area array) solder bumps were introduced. With advanced package designs, these redistribution layers move from the circuit board to the package.
The arrival of these new structures and components, TSVs, microbumps, pillars, and in-chip redistribution layers have all created new process control challenges for manufacturers.
The only way to ensure the geometries is to measure. These new structures add new steps to process development.
Nanometrics UniFire system provides the answer to these metrology challenges, providing precise measurements of top and bottom CD for high aspect ratio TSVs. Using versatile white light interferometry, the UniFire is equally capable of providing data on via depth, and can even provide inspection in the etch process capable of finding scratches, residue and blocked vias.
For bump and redistribution layer metrology, the UniFire system offers a typical height repeatability at 1σ < 50nm , and typical CD repeatability at 1σ< 20nm. The system provides the user the ability to measure copper/ bump height and coplanarity, as well as the ability to measure electroplate defects such as missing or bridged bumps.
Adding to these capabilities, the UniFire extracts multiple CD metrics in a single measurement, allowing for the capture of bottom and top CD, profile, height and roughness data for under bump metallization.
SPARK – Defect Inspection
The newest member of the Nanometrics’ product family is the SPARK defect inspection system. The SPARK system adds new, complementary capabilities to Nanometrics process control suite, including defects associated with wafer bonding, thinning and backside processing, as well as TSV formation. The SPARK system can inspect the TSV formation process post etch, clean, oxide and barrier layer deposition. Using both brightfield and darkfield inspection channels, the tool detects particles on the surface and buried in the layers. The SPARK system maps the defects of interest and allows the user to focus on “killer” defects that can create risk for subsequent process steps.
A new and fundamental step associated with advanced 3D packaging, is the bonding of wafers. To create 3D packages device wafers are thinned, bonded to a carrier with glue, and then polished down to the desired thickness. Any residual defects in that bond are important. Since thinned wafers can be as little as 50µm, a glue bubble, particle or other abnormality will lift it up locally, making polishing more complicated since it is likely that the wafer area over the glue bubble will be over or under polished.
The same is true for wafer-to-wafer bonding. In both cases, gaps in the glue layer may cause surfaces to be pushed apart, or (after passing through thermal treatments) can cause the wafer to be susceptible to cracking.
Th SPARK is uniquely capable of providing this information. The system detects and distinguishes between different types of bonding layer defects including air bubbles, embedded particles and delamination.